1. Technical Field of the Invention
The present invention relates to a method for fabricating MOS-FET (field-effect transistor) using a SOI (Silicon On Insulator) type semiconductor substrate.
2. Description of the Background Art
A SOI substrate is a substrate in which a silicon single-crystal layer is formed on a silicon substrate with an insulating film layer formed on a surface layer portion. By forming a MOS transistor on the SOI substrate, characteristics improvement and reduction in a parasitic capacity are promoted, and a device capable of operation at a low voltage can be obtained.
There are two types of SOI layer in the SOI substrate: a fully depleted type and a partial depleted type. The fully depleted type SOI has the whole SOI layer depleted. On the other hand, the partial depleted type SOI partially has a portion not depleted. In order to make best of the characteristics of the SOI device that the parasitic capacity between a device and a substrate can be reduced and the like, the fully depleted type is more advantageous.
In the fully depleted type SOI, a lowered voltage and reduction in a load capacity can be realized at the same time, but the thickness of a silicon layer (SOI layer) forming a transistor with a threshold voltage applicable to a circuit is 50 nm or less.
In order to reduce an off-leak current and to increase the threshold value, it is necessary to increase an impurity concentration in a channel region. However, if the impurity concentration in the channel region is increased, the maximum depleted layer width is reduced and formation of the fully depleted type transistor becomes difficult.
According to the invention described in Japanese Patent Laid-Open No. 2000-349295, a position of a peak value of the impurity concentration in the channel region is set at a position shallower than a depth where the impurity concentration exceeds a carrier concentration in an inversion layer. The impurity concentration on the surface of the channel region becomes higher than that in a buried insulating film. By this arrangement, the fully depleted type transistor whose threshold voltage is increased while the off-leak current is reduced can be obtained.
A fabricating method disclosed in Japanese Patent Laid-Open No. 2000-349295 proposes a method for controlling a peak position of an implanted impurity and for epitaxial growth of a high-concentration layer using etching of a dummy layer or the SOI layer corresponding to the thickness of the dummy layer.
The method using the dummy layer is accompanied by fluctuation of the impurity peak position in a wafer face when the impurity is ion-implanted. Thus, in order to restrain the fluctuation in a dose amount of the impurity to be implanted, the peak of the implanted impurity needs to be at a sufficiently deep position in the SOI layer. Thus, application of the method to the fully depleted type SOI having a thin SOI layer with the thickness of 50 nm or less is difficult.
In the method using etching of the silicon layer corresponding to the dummy layer, there is a problem that the dose amount in the channel region is fluctuated by fluctuation of the etching. The method using the epitaxial growth has a problem that a throughput is poor with the growth under the condition that a single crystal SOI layer is sufficiently obtained.